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| 1 file number 4284.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. intercast? is a trademark of intel corporation. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hmp8170, hmp8171, hmp8172, hmp8173 ntsc/pal video encoder the hmp8170, hmp8171, hmp8172, and hmp8173 ntsc and pal encoders are designed for use in systems requiring the generation of high-quality ntsc and pal video. ycbcr digital video data drive the p0-p15 inputs. the y data is optionally lowpass filtered to 6mhz and drives the y analog output. cb and cr are each lowpass filtered to 1.3mhz, quadrature modulated, and added together. the result drives the c analog output. the digital y and c data are also added together and drive the two composite analog outputs. the dacs can drive doubly-terminated (37.5 w ) lines, and run at a 2x oversampling rate to simplify the analog output ?lter requirements. applications ? dvd players ? video cd players ? digital vcrs ? multimedia pcs related products ? ntsc/pal encoders - hmp8154, hmp8156a ? ntsc/pal decoders - hmp8115 features ? (m) ntsc and (b, d, g, h, i, m, n, nc) pal operation ? bt.601 and square pixel operation ? digital input formats - 8-bit, 16-bit 4:2:2 ycbcr - 8-bit bt.656 ? analog output formats - y/c + two composite - rgb + composite - yuv + composite ? flexible video timing control - timing master or slave - selectable polarity on each control signal - programmable blank output timing ? sliced vbi data support - closed captioning - widescreen signalling (wss) - bt.653 system b and c teletext - nabts (north american broadcast teletext) - wst (world system teletext) ? four 2x oversampling, 10-bit dacs ? fast i 2 c interface ordering information part number macrovision v7.01 rgb / yuv outputs temp. range ( o c) package pkg. no. hmp8170cn no no 0 to 70 64 ld pqfp (note 2) q64.14x14 hmp8171cn (note 1) yes no 0 to 70 64 ld pqfp (note 2) q64.14x14 hmp8172cn no yes 0 to 70 64 ld pqfp (note 2) q64.14x14 HMP8173CN (note 1) yes yes 0 to 70 64 ld pqfp (note 2) q64.14x14 hmp817xeval1 daughter card evaluation platform, where x is replaced by 0, 1, 2, or 3 (note 3). notes: 1. the hmp8171 and hmp8173 may be purchased by macrovision authorized buyers only. these devices are protected by u.s. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual property rights. the use of macrovisions copy protection technology in the devices must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorize d in writing by macrovision. reverse engineering or disassembly is prohibited. 2. pqfp is also known as qfp and mqfp. 3. evaluation board descriptions are in the applications section. data sheet may 1999
2 functional block diagram sa scl sda reset host interface p0 - p15 4:2:2 to 4:4:4 sample conversion (optional) lp filter y cb/cr vbi data processing dac dac dac dac y ntsc/ ntsc/ c pal 1 pal 2 hsync vsync blank clk video timing clk2 field control vref fs adjust internal 1.195v reference 2 x upsample chroma modulation lp filter (4:4:4 to 8:8:8) macrovision processing (hmp8171 and hmp8173 only) hmp8170, hmp8171, hmp8172, hmp8173 3 functional operation the hmp8170 - hmp8173 are fully integrated digital encoders. all accept ycbcr digital video input data and generate analog video output signals. the four outputs are two composite video signals and y/c (s-video). the hmp8172 and hmp8173 can also be con?gured to output one composite and component rgb or yuv video. the hmp817x accepts pixel data in one of several formats and transforms it into 4:4:4 sampled luminance and chrominance (ycbcr) data. the encoder then interpolates the ycbcr data to twice the pixel rate and low pass filters it to match the bandwidth of the video output format. if enabled, the encoder also adds vertical blanking interval (vbi) information to the y data. at the same time, the encoder modulates the chrominance data with a digitally synthesized subcarrier. finally, the encoder outputs luminance, chrominance, and their sum as analog signals using 10-bit d/a converters. the hmp817x provides operating modes to support all versions of the ntsc and pal standards and accepts full size input data with rectangular (bt.601) and square pixel aspect ratios. it operates from a single clock at twice the pixel clock rate determined by the operating mode. the hmp817xs video timing control is ?exible. it may operate as the master, generating the systems video timing control signals, or it may accept external timing controls. the polarity of the timing controls and the number of active pixels and lines are programmable. pixel data input the hmp817x accepts bt.601 ycbcr pixel data via the p0-p15 input pins. the de?nition of each pixel input pin is determined by the input format selected in the input format register. the de?nition for each mode is shown in table 1. the ycbcr luminance and color difference signals are each 8 bits, scaled 0 to 255. the nominal range for y is 16 (black) to 235 (white). y values less than 16 are clamped to 16; values greater than 235 are processed normally. the nominal range for cb and cr is 16 to 240 with 128 representing zero. cb and cr values outside their nominal range are processed normally. note that when converted to the analog outputs, some combinations of ycbcr outside their nominal ranges would generate a composite video signal larger than the analog output limit. the composite signal will be clipped, but the s-video outputs (y and c) will note be. the color difference signals are time multiplexed into one 8-bit bus beginning with a cb sample. the y and cbcr busses may be input in parallel (16-bit mode) or may be time multiplexed and input as a single bus (8-bit mode). the single bus may also contain sav and eav video timing reference codes or ancillary data (bt.656 mode). pixel input and control signal timing the pixel input timing and the video control signal input/output timing of the hmp817x depend on the parts operating mode. the periods when the encoder samples its inputs and generates its outputs are summarized in table 2. figures 1, 2, and 3 show the timing of clk, clk2, blank, and the pixel input data with respect to each other. blank may be an input or an output; the ?gures show both. when it is an input, blank must arrive coincident with the pixel input data; all are sampled at the same time. when blank is an output, its timing with respect to the pixel inputs depends on the blank timing select bit in the timing_i/o_1 register. if the bit is cleared, the hmp817x negates blank one clk cycle before it samples the pixel inputs. if the bit is set, the encoder negates blank during the same clk cycle in which it samples the input data. in effect, the input data must arrive one clk cycle earlier than when the bit is cleared. this mode is not shown in the ?gures. table 1. pixel data input formats pin name 16-bit 4:2:2 ycbcr 8-bit 4:2:2 ycbcr bt.656 p0 p1 p2 p3 p4 p5 p6 p7 cb0, cr0 cb1, cr1 cb2, cr2 cb3, cr3 cb4, cr4 cb5, cr5 cb6, cr6 cb7, cr7 ignored p8 p9 p10 p11 p12 p13 p14 p15 y0 y1 y2 y3 y4 y5 y6 y7 y0, cb0, cr0 y1, cb1, cr1 y2, cb2, cr2 y3, cb3, cr3 y4, cb4, cr4 y5, cb5, cr5 y6, cb6, cr6 y7, cb7, cr7 ycbcr data, sav and eav sequences, and ancillary data table 2. pixel input and control signal i/o timing input format input pixel data sample video timing control (note) clk frequency input sample output on input output 16-bit ycbcr rising edge of clk2 when clk is low rising edge of clk2 when clk is high. one-half clk22 8-bit ycbcr every r ising edge of clk2 every rising edge of clk2 any rising edge of clk2 ignored one-half clk2 bt.656 every r ising edge of clk2 not allowed any rising edge of clk2 ignored one-half clk2 note: video timing control signals include hsync, vsync, blank and field. the sync and blanking i/o directions are independent; field is always an output. hmp8170, hmp8171, hmp8172, hmp8173 4 8-bit ycbcr format when 8-bit ycbcr format is selected, the data is latched on each rising edge of clk2. the pixel data must be [cb y cr y cb y cr y . . . ], with the first active data each scan line being cb data. the pixel input timing is shown in figure 1. as inputs, blank, hsync, and vsync are latched on each rising edge of clk2. as outputs, blank, hsync, and vsync are output following the rising edge of clk2. if the clk pin is con?gured as an input, it is ignored. if con?gured as an output, it is one-half the clk2 frequency. 16-bit ycbcr format when 16-bit ycbcr format is selected, the pixel data is latched on the rising edge of clk2 while clk is low. the pixel input timing is shown in figure 2. as inputs, blank, hsync, and vsync are latched on the rising edge of clk2 while clk is low. as outputs, hsync, vsync, and blank are output following the rising edge of clk2 while clk is high. in these modes of operation, clk is one-half the clk2 frequency. 8-bit bt.656 format when bt.656 format is selected, data is latched on each rising edge of clk2. the pixel input timing is shown in figure 3. the ?gure shows the eav code at the end of the line. the format of the sav and eav codes are shown in table 3. the bt.656 input may also include ancillary data to load the vbi or rtci data registers. the hmp817x will use the ancillary data when enabled in the vbi data input and timing i/o registers. the ancillary data formats and the enable registers are described later in this data sheet. as inputs, the blank, hsync, and vsync pins are ignored since all timing is derived from the eav and sav sequences within the data stream. as outputs, blank, hsync and vsync are output following the rising edge of clk2. if the clk pin is con?gured as an input, it is ignored. if con?gured as an output, it is one-half the clk2 frequency. figure 1. pixel input timing - 8-bit ycbcr figure 2. pixel input timing - 16-bit ycbcr cb 0 y 0 cr 0 y 1 cb 2 y 2 clk2 p8-p15 blank (input) y n blank (output) y 0y 1y 2y 3y 4y 5 clk p8-p15 blank (input) cb 0 cr 0 cb 2 cr 2 cb 4 cr 4 p0-p7 clk2 y n cr n-1 blank (output) hmp8170, hmp8171, hmp8172, hmp8173 5 video timing control the pixel input data and the output video timing of the hmp817x are at 50 or 59.94 ?elds per second interlaced. the timing is controlled by the blank, hsync, vsync, field, and clk2 pins. hsync, vsync, and field timing the leading edge of hsync indicates the beginning of a horizontal sync interval. if hsync is an output, it is asserted for about 4.7 m s. if hsync is an input, it must be active for at least two clk2 periods. the width of the analog horizontal sync tip is determined from the video standard and does not depend on the width of hsync. the leading edge of vsync indicates the beginning of a vertical sync interval. if vsync is an output, it is asserted for 3 scan lines in (mm) ntsc and (m, n) pal modes or 2.5 scan lines in (b, d, g, h, i, nc) pal modes. if vsync is an input, it must be asserted for at least two clk2 periods. when hsync and vsync are con?gured as outputs, their leading edges will occur simultaneously at the start of an odd ?eld. at the start of an even ?eld, the leading edge of vsync occurs in the middle of the line. when hsync and vsync are con?gured as inputs, the hmp817x provides a programmable hsync window for determining field. the window is speci?ed with respect to the leading or trailing edge of vsync. the edge is selected in the ?eld control register. when hsync is found inside the window, then the encoder sets field to the value speci?ed in the ?eld control register. the hmp817x provides programmable timing for the vsync input. at the active edge of vsync, the encoder resets its vertical half-line counter to the value speci?ed by the ?eld control register. this allows the input and output syncs to be offset, although the data must still be aligned. the field signal is always an output and changes state near each leading edge of vsync. the delay between the syncs and field depends on the encoders operating mode as summarized in table 4. in modes in which the encoder uses clk to gate its inputs and outputs, the field signal may be delayed 0-12 additional clk2 periods. figure 4 illustrates the hsync, vsync, and field general timing for (m) ntsc and (m, n) pal. figure 5 illustrates the general timing for (b, d, g, h, i, nc) pal. in the ?gures, all the signals are shown active low (their reset state), and field is low during odd ?elds. figure 3. pixel input timing - bt.656 cb 2 y 2 cr 2 y 3 cb 4 y 4 clk2 p8-p15 "ff" "00" blank (output) "00" eav "10" "10" "80" table 3. bt.656 eav and sav sequences pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble word 1 1 1 1 1 1 1 1 1 preamble word 2 0 0 0 0 0 0 0 0 preamble word 3 0 0 0 0 0 0 0 0 status word 1 f v h p3 p2 p1 p0 notes: f: 0 = field 1; 1 = field 2 v: 0 = active line; 1 = vertical blanking h: 0 = start active video; 1 = end active video p3 - p0: protection bits; ignored table 4. field output timing operating mode clk2 delay comments sync i/o direction blank i/o direction input input 148 field lags vsync switching from odd to even. field lags the earlier of vsync and hsync when syncs are aligned when switching from even to odd. input output 138 field lags vsync. output dont care 32 field leads vsync. hmp8170, hmp8171, hmp8172, hmp8173 6 blank timing the encoder uses the hsync, vsync, field signals to generate a standard composite video waveform with no active video (black burst). the signal includes only sync tips, color burst, and optionally, a 7.5 ire blanking setup. based on the blank signal, the encoder adds the pixel input data to the video waveform. the encoder ignores the pixel input data when blank is asserted. instead of the input data, the encoder generates the blanking level. the encoder also ignores the pixel inputs when generating vbi data on a speci?c line, even if blank is negated. there must be an even number of active and total pixels per line. in the 8-bit ycbcr modes, the number of active and total pixels per line must be a multiple of four. note that if blank is an output, half-line blanking on the output video cannot be done. the hmp817x never adds a 7.5 ire blanking setup during the active line time on scan lines 1-21 and 263-284 for (m) ntsc, scan lines 523-18 and 260-281 for (m) pal, and scan lines 623-22 and 311-335 for (b, d, g, h, i, n) pal, allowing the generation of video test signals, timecode, and other information by controlling the pixel inputs appropriately. the relative timing of blank, hsync, and the output video depends on the blanking and sync i/o directions. the typical timing relation is shown in figure 6. the delays which vary with operating mode are indicated. the width of the composite sync tip and the location and duration of the color burst are ?xed based on the video format. . when blank is an output, the encoder asserts it during the inactive portions of active scan lines (horizontal blanking) and for all of each inactive scan line (vertical blanking). the inactive scan lines blanked each ?eld are determined by the start_v_blank and end_v_blank registers. the inactive portion of active scan lines is determined by the start_h_blank and end_h_blank registers. the zero count for horizontal blanking is 32 clk2 cycles before the 50% point of the composite sync. from this zero point, the hmp817x counts every other clk2 cycle. when the count reaches the value in the start_h_blank register, the encoder negates blank. when the count reaches the value in the end_h_blank register, blank is asserted. there may be an additional 0-3 clk2 delays in modes which use clk. the data pipeline delay through the hmp817x is 26 clk2 cycles. in operating modes which use clk to gate the inputs into the encoder, the delay may be an additional 0-7 clk2 cycles. the delay from blank to the start or end of active video is an additional one-half clk cycle when the blank timing select bit is cleared. the active video may also appear to end early or start late since the hmp817x controls the blanking edge rates. figure 4a. beginning an odd field figure 4b. beginning an even field figure 4. hsync, vsync, and field timing for (m) ntsc and (m, n) pal figure 5a. beginning an odd field figure 5b. beginning an even field figure 5. hsync, vsync, and field timing for (b, d, g, h, i, nc) pal hsync vsync field hsync vsync field hsync vsync field hsync vsync field figure 6. hsync, blank, and output video timing, normal mode blank composite video out hsync sync delay start h blank data pipe delay hmp8170, hmp8171, hmp8172, hmp8173 7 the delay from the active edge of hsync to the 50% point of the composite sync is 4-39 clk2 cycles depending on the hmp817x operating mode. the delay is shortest when the encoder is the timing master; it is longest when in slave mode. clk2 input timing the clk2 input clocks all of the hmp817x, including its video timing counters. for proper operation, all of the hmp817x inputs must be synchronous with clk2. the frequency of clk2 depends on the devices operating mode and the total number of pixels per line. the standard clock frequencies are shown in table 5. note that the color subcarrier is derived from the clk2 input. any jitter on clk2 will be transferred to the color subcarrier, resulting in color changes. just 400ps of jitter on clk2 causes up to a 1 degree color subcarrier phase shift. thus, clk2 should be derived from a stable clock source, such as a crystal. the use of a pll to generate clk2 is not recommended. video processing upsampling the encoder begins the video processing with the pixel input data. it converts the 4:2:2 ycbcr data to 4:4:4 data. the conversion is done by 2x upsampling the cb and cr data. the cbcr upsampling function uses linear interpolation. the hmp817x then upsamples the 4:4:4 data to generate 8:8:8 data. again, the encoder uses linear interpolation for the upsampling. horizontal filtering unless disabled, the hmp817x lowpass ?lters the y data to 6.0mhz. lowpass ?ltering y removes any aliasing artifacts due to the upsampling process, and simpli?es the analog output ?lters. the y 6.0mhz lowpass ?lter response is shown in figure 7. at this point, the hmp817x also scales the y data to generate the proper output levels for the various video standards. the hmp817x lowpass filters the cb and cr data to 1.3mhz prior to modulation. the lowpass filtering removes any aliasing artifacts due to the upsampling process (simplifying the analog output filters) and also properly bandwidth-limits cb and cr prior to modulation. the chrominance filtering is not optional like luminance filtering. the cb and cr 1.3mhz lowpass filter response is shown in figure 8. table 5. typical video timing parameters video standard pixels per line hblank register values vblank register values clk2 (mhz) total active start end start end rectangular pixels (bt.601) (m) ntsc (b, d, g, h, i) pal (m) pal (n) pal (nc) pal 858 864 858 864 864 720 720 720 720 720 842 (0x34a) 853 (0x355) 842 (0x34a) 853 (0x355) 853 (0x355) 122 (0x7a) 133 (0x85) 122 (0x7a) 133 (0x85) 133 (0x85) 259 (0x103) 310 (0x136) 259 (0x103) 309 (0x135) 310 (0x136) 19 (0x13) 22 (0x16) 19 (0x13) 21 (0x15) 22 (0x16) 27.0 27.0 27.0 27.0 27.0 square pixels (m) ntsc (b, d, g, h, i) pal (m) pal (n) pal (nc) pal 780 944 780 944 944 640 768 640 768 768 758 (0x2f6) 923 (0x39b) 758 (0x2f6) 923 (0x39b) 923 (0x39b) 118 (0x76) 155 (0x9b) 118 (0x76) 155 (0x9b) 155 (0x9b) 259 (0x103) 310 (0x136) 259 (0x103) 309 (0x135) 310 (0x136) 19 (0x13) 22 (0x16) 19 (0x13) 21 (0x15) 22 (0x16) 24.54 29.5 24.54 29.5 29.5 hmp8170, hmp8171, hmp8172, hmp8173 8 . color subcarrier generation the hmp817x uses a numerically controlled oscillator (nco) clocked by clk2 and a sine look up rom to generate the color subcarrier. as shown in figure 9, the phase increment value (phinc) of the nco may come from the encoders internal look up table, bt.656 ancillary data, or a control register. the phinc source is selected in timing i/o register 2. . figure 7a. full spectrum figure 7b. pass band figure 7. y lowpass filter response ntsc square pixel clk2 = 24.54mhz ntsc or pal clk2 = 27.00mhz pal square pixel clk2 = 29.50mhz rectangular pixel 0 -10 -20 -30 -40 -50 -60 0 2 4 6 8 10 12 14 frequency (mhz) attenuation (db) 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 012345 67 attenuation (db) frequency (mhz) ntsc square pixel clk2 = 24.54mhz ntsc or pal clk2 = 27.00mhz pal square pixel clk2 = 29.50mhz rectangular pixel figure 8a. full spectrum figure 8b. pass band figure 8. cb and cr lowpass filter response 024681012 frequency (mhz) 0 -10 -20 -30 -40 -50 -60 attenuation (db) ntsc square pixel clk2 = 24.54mhz ntsc or pal clk2 = 27.00mhz rectangular pixel pal square pixel clk2 = 29.50mhz 0 0.2 0.4 0.6 0.8 1.0 1.2 frequency (mhz) 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 attenuation (db) ntsc square pixel clk2 = 24.54mhz ntsc or pal clk2 = 27.00mhz rectangular pixel -3.5 -4.0 1.4 1.6 pal square pixel clk2 = 29.50mhz figure 9. color subcarrier generation nco. + internal bt.656 i 2 c phinc select phinc d q clk2 nco reset phint hmp8170, hmp8171, hmp8172, hmp8173 9 the msbs of the accumulated phase value (phint) are used to address the encoders sine look up rom. the sine values from the rom are pre-scaled to generate the proper levels for the various video standards. prescaling outside the cbcr data path minimizes color processing artifacts. the hmp817x modulates the ?ltered 8:8:8 chrominance data with the synthesized subcarrier. the sch phase is 0 degrees after reset but then changes monotonically over time due to residue in the nco. in an ideal system, zero sch phase would be maintained forever. in reality, this is impossible to achieve due to pixel clock frequency tolerances and digital rounding errors. when the phinc source is bt.656 data, the sch phase reset should be disabled. if enabled, the hmp817x resets the nco periodically to avoid an accumulation of sch phase error. the reset occurs at the beginning of each ?eld to burst phase sequence. the sequence repeats every 4 ?elds for ntsc or 8 ?elds for pal. resetting the sch phase every four ?elds (ntsc) or eight ?elds (pal) avoids the accumulation of sch phase error at the expense of requiring any ntsc/pal decoder after the encoder be able to handle very minor jumps (up to 2 degrees) in the sch phase at the beginning of each four- ?eld or eight-?eld sequence. most ntsc/pal decoders are able to handle this due to video editing requirements. composite video limiting the hmp817x adds the luminance and modulated chrominance together with the sync, color burst, and optional blanking pedestal to form the composite video data. if enabled in the video processing register, the encoder limits the active video so that it is always greater than one-eighth of full scale. this corresponds to approximately one-half the sync height. this allows the generation of safe video in the event non-standard ycbcr values are input to the device. controlled edges the ntsc and pal video standards specify edge rates and rise and fall times for portions of the video waveform. the hmp817x automatically implements controlled edge rates and rise and fall times on these edges: 1. analog horizontal sync (rising and falling edges) 2. analog vertical sync interval (rising and falling edges) 3. color burst envelope 4. blanking of analog active video 5. closed captioning information 6. wss information 7. teletext information sliced vbi data the hmp817x generates three types of vertical blanking interval data: closed captioning, widescreen signalling, and teletext data. the data is generated on the scan lines speci?ed by the selected output video standard which are enabled in the vbi data control register. during scan lines with vbi data, the pixel inputs are ignored. closed captioning (cc) the hmp817x captioning data output includes clock run-in and start bits followed by the captioning data. during closed captioning encoding, the pixel inputs are ignored on the scan lines containing captioning information. the hmp817x has two 16-bit registers containing the captioning information. each 16-bit register is organized as two cascaded 8-bit registers. one 16-bit register (caption 21) is read out serially during line 18, 21 or 22; the other 16-bit register (wss 284) is read out serially during line 281, 284 or 335. the data registers are shifted out lsb ?rst. the captioning output level is 50 ire for a logic 1 and 0 ire for a logic 0. all transitions between levels are controlled to have a raised-cosine shape. the rise or fall time of any transition is 240-288ns. the caption data registers may be loaded via the i 2 c interface or as bt.656 ancillary data. table 6 illustrates the format of the caption data as bt.656 ancillary data. the transfer should occur only once per field before the start of the sav sequence of the line containing the captioning output. when written via the i 2 c interface, the bytes may be written in any order but both must be written within one frame time for proper operation. if the registers are not updated, the encoder resends the previously loaded values. the hmp817x provides a write status bit for each captioning line. the encoder clears the write status bit to 0 when captioning is enabled and both bytes of the captioning data register have been written. the encoder sets the write status bit to 1 after it outputs the data, indicating the registers are ready to receive new data. captioning information may be enabled for either line, both lines, or no lines. the captioning modes are summarized in table 7. hmp8170, hmp8171, hmp8172, hmp8173 10 widescreen signalling (wss) the hmp817x wss data output includes clock run-in and start codes followed by the wss data. for ntsc operation, the wss data is followed by six bits of crc data. the hmp817x has two 14-bit registers containing the wss information and two 6-bit registers containing the wss crc data. each 14-bit register is organized as a 6-bit register cascaded with an 8-bit one. one 14-bit register (wss 20) is read out serially during line 17, 20 or 23; the other 14-bit register (caption 283) is read out serially during line 280, 283 or 336. the data registers are shifted out lsb ?rst. the wss output level depends on the video format. for ntsc operation (eiaj cpx-1204), the wss output level is 70 ire for a logic 1 and 0 ire for a logic 0. all transitions between levels are controlled to have a raised-cosine shape with a rise or fall time of 240ns. for pal operation (itu-r bt.1119), the wss output level is 71.5 ire for a logic 1 and 0 ire for a logic 0. all transitions between levels are controlled to have a raised-cosine shape with a rise or fall time of 118ns. the wss data registers may be loaded via the i 2 c interface or as bt.656 ancillary data. table 8 illustrates the format of the wss data as bt.656 ancillary data. the transfer should occur only once per ?eld before the start of the sav sequence of the line containing the wss output. when written via the i 2 c interface, the bytes may be written in any order but all three bytes of each enabled line must be written within one frame time for proper operation. if the registers are not updated, the encoder resends the previously loaded values. the hmp817x provides a write status bit for each wss line. the encoder clears the write status bit to 0 when wss is enabled and all bytes of the wss data register have been written. the encoder sets the write status bit to 1 after it outputs the data, indicating the registers are ready to receive new data. wss information may be enabled for either line, both lines, or no lines. the wss modes are summarized in table 9. table 6. bt.656 ancillary data format for closed captioning data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 1 0 0 0 0 0 0 0 0 preamble 2 1 1 1 1 1 1 1 1 preamble 3 1 1 1 1 1 1 1 1 data id ep# ep 1 1 0 0 0 line data block number ep# ep 0 0 0 0 0 1 data word count ep# ep 0 0 0 0 0 1 caption register byte 3 ep# ep 0 0 bit 15 bit 14 bit 13 bit 12 caption register byte 1 ep# ep 0 0 bit 11 bit 10 bit 9 bit 8 caption register byte 1 ep# ep 0 0 bit 7 bit 6 bit 5 bit 4 caption register byte 0 ep# ep 0 0 bit 3 bit 2 bit 1 bit 0 crc p14# x x x x x x x notes: the even parity (ep and ep#) bits are ignored. line = data register select: 0 = line 21; 1 = 284. x = dont care. table 7. closed captioning modes closed captioning enable bits output line(s) captioning register write status bit 284a 284b 21a 21b 284 21 00 none ignored ignored always 1 always 1 01 21 (ntsc) 18 (m pal) 22 (other pal) ignored caption data always 1 0 = loaded 1 = output 10 284 (ntsc) 281 (m pal) 335 (other pal) caption data ignored 0 = loaded 1 = output always 1 11 21, 284 (ntsc) 18, 281 (m pal) 22, 335 (other pal) caption data caption data 0 = loaded 1 = output 0 = loaded 1 = output hmp8170, hmp8171, hmp8172, hmp8173 11 teletext the hmp817x supports itu-r bt.653 625-line and 525-line teletext system b and c generation. wst (world system teletext) is the same as bt.653 system b. nabts (north american broadcast teletext speci?cation) is the same as bt.653 525-line system c. nabts is also used to transmit intel intercast information. during the teletext encoding, the lines pixel inputs are ignored. the teletext information includes a 16-bit clock synchronization code; the hmp817x automatically generates it. the teletext output level depends on the video format. for system b teletext, the output level is 66 ire for a logic 1 and 0 ire for a logic 0. all transitions between levels are controlled to have a raised-cosine shape with a rise or fall time of 200ns. for system c teletext, the output level is 70 ire for a logic 1 and 0 ire for a logic 0. all transitions between levels are controlled to have a raised-cosine shape with a rise or fall time of 200ns. the hmp817x generates teletext output on any scan line that includes teletext data in that lines bt.656 ancillary data. the encoder must receive the ancillary data before the sav sequence in order to output the teletext data. table 10 shows the bt.656 ancillary data format for loading the teletext data registers. table 8. bt.656 ancillary data format for widescreen signalling data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 1 0 0 0 0 0 0 0 0 preamble 2 1 1 1 1 1 1 1 1 preamble 3 1 1 1 1 1 1 1 1 data id ep# ep 1 1 0 0 1 line data block number ep# ep 0 0 0 0 0 1 data word count ep# ep 0 0 0 0 1 0 wss data nibble 3 ep# ep 0 0 0 0 bit 13 bit 12 wss data nibble 2 ep# ep 0 0 bit 11 bit 10 bit 9 bit 8 wss data nibble 1 ep# ep 0 0 bit 7 bit 6 bit 5 bit 4 wss data nibble 0 ep# ep 0 0 bit 3 bit 2 bit 1 bit 0 wss crc nibble 1 ep# ep 0 0 0 0 bit 5 bit 4 wss crc nibble 0 ep# ep 0 0 bit 3 bit 2 bit 1 bit 0 reserved ep# ep 0 0 0 0 0 0 reserved ep# ep 0 0 0 0 0 0 crc p14# x x x x x x x notes: the even parity (ep and ep#) bits are ignored. line = data register select: 0 = line 20; 1 = 283. the wss crc data bits are ignored during pal operation but must be included in the transfer. x = dont care. table 9. widescreen signalling modes wss enable bits output line(s) wss registers write status bit 283a, 283b, crc283 20a, 20b, crc20 283 20 00 none ignored ignored always 1 always 1 01 20 (ntsc) 17 (m pal) 23 (other pal) ignored wss data always 1 0 = loaded 1 = output 10 283 (ntsc) 280 (m pal) 336 (other pal) wss data ignored 0 = loaded 1 = output always 1 11 20, 283 (ntsc) 17, 280 (m pal) 23, 336 (other pal) wss data wss data 0 = loaded 1 = output 0 = loaded 1 = output note: the crc registers are always ignored during pal operation. hmp8170, hmp8171, hmp8172, hmp8173 12 table 10. bt.656 ancillary data format for teletext data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 1 0 0 0 0 0 0 0 0 preamble 2 1 1 1 1 1 1 1 1 preamble 3 1 1 1 1 1 1 1 1 data id ep# ep 1 1 0 1 0 0 data block number ep# ep 0 0 0 0 0 1 data word count ep# ep 0 1 0 1 1 0 teletext register data (86 nibbles) ep# ep line sys bit 343 bit 342 bit 341 bit 340 ep# ep 0 0 bit 339 bit 338 bit 337 bit 336 . . . ep# ep 0 0 bit 7 bit 6 bit 5 bit 4 ep# ep 0 0 bit 3 bit 2 bit 1 bit 0 reserved ep# ep 0 0 0 0 0 0 reserved ep# ep 0 0 0 0 0 0 crc p14# x x x x x x x notes: the even parity (ep and ep#) bits are ignored. line = standard select: 0 = 525 lines; 1 = 625 lines sys = system select: 0 = system b; 1 = system c. 625-line system b uses 43 bytes; all bits are used. 525-line system b uses 35 bytes; bits 343-280 are ignored. 525-line system c uses 34 bytes; bits 343-272 are ignored. x = dont care. table 11. bt.656 ancillary data format for phinc data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 1 0 0 0 0 0 0 0 0 preamble 2 1 1 1 1 1 1 1 1 preamble 3 1 1 1 1 1 1 1 1 data id ep# ep 1 1 0 1 0 1 data block number ep# ep 0 0 0 0 0 1 data word count ep# ep 0 0 0 0 1 1 hpll increment (4 nibbles) ep# ep 0 0 bit 15 bit 14 bit 13 bit 12 ep# ep 0 0 bit 11 bit 10 bit 9 bit 8 ep# ep 0 0 bit 7 bit 6 bit 5 bit 4 ep# ep 0 0 bit 3 bit 2 bit 1 bit 0 fscpll increment (8 nibbles) ep# ep psw 0 bit 31 bit 30 bit 29 bit 28 ep# ep f2 f1 bit 27 bit 26 bit 25 bit 24 . . . ep# ep 0 0 bit 7 bit 6 bit 5 bit 4 ep# ep 0 0 bit 3 bit 2 bit 1 bit 0 crc p14# x x x x x x x notes: the even parity (ep and ep#) bits are ignored. hpll, psw, f2, and f1 are ignored. x = dont care. hmp8170, hmp8171, hmp8172, hmp8173 13 macrovision the hmp8171 and hmp8173 provide the copy protection system specified by the macrovision antitaping process for digital platforms document, revision 7.01, september 6, 1996. the devices are protected by u.s. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual property rights. the use of macrovisions copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. additional information about macrovision in the hmp8171 and hmp8173 is available to macrovision authorized buyers only. tech brief 359, hmp8171/hmp8173 macrovision registers provides the details required. analog outputs the hmp817x converts the video data into analog signals using four 10-bit dacs running at the clk2 rate. the dacs output a current proportional to the digital data. the full scale output current is determined by the reference voltage vref and an external resistor rset. the full scale output current is given by: i fullscale (ma) = 3.9 * vref (v)/rset (k w ) (eq 1.) vref must be chosen such that it is within the parts operating range; rset must be chosen such that the maximum output current is not exceeded. if the vref pin is not connected, the hmp817x uses the internal reference voltage. otherwise, the applied voltage overdrives the internal reference. if an external reference is used, it must decoupled from any power supply noise. an example external reference circuit is shown in the applications section. the hmp817x generates 1v p-p nominal video signals across 37.5 w loads, corresponding to doubly terminated 75 w lines. the encoder may also drive larger loads. the full scale output current and load must be chosen such that the maximum output voltage is not exceeded. output dac filtering since the dacs run at 2x the pixel sample rate, the sin(x)/x rolloff of the outputs is greatly reduced, and there are fewer high frequency artifacts in the output spectrum. this allows using simple analog output ?lters. the analog output ?lter should be ?at to f s /4 and have good rejection at 3f s /4. example ?lters are shown in the applications section. composite + y/c output mode the hmp817x provides composite with s-video output mode. when s-video outputs are selected, the encoder outputs the luminance, modulated chrominance, and two copies of the composite video signals. all four outputs are time aligned. the output pin assignments are summarized in table 12. composite + rgb output mode the hmp8172/hmp8173 also provide composite with component rgb output mode. when analog rgb video is selected, the hmp817x transforms the filtered 8:8:8 ycbcr data into 8:8:8 rgb data. the transform matrix uses different coefficients to generate ntsc or pal video levels. the analog rgb outputs have a range of 0.3-1.0v with an optional blanking pedestal. composite sync information (0.0-0.3v) may be optionally added to the green output. vbi data is not included on the rgb outputs. the hmp817x also generates composite video when in rgb output mode. all four outputs are time aligned. the hmp817x provides selectable pin outs for the rgb outputs. when the scart compatibility bit is cleared, the analog composite video is output onto the ntsc/pal 1 pin. red information is output onto the ntsc/pal 2 pin, blue information is output onto the c pin, and green information is output onto the y pin. when the bit is set, the analog composite video is output onto the y pin. red information is output onto the c pin, blue video is output on the ntsc/pal 2 pin, and the green signal is output on the ntsc/pal 1 pin. the output pin assignments are summarized in table 12. table 12. output pin assignments pin name pin # output mode (scart select bit) comp. with y/c (x) comp. w/ rgb (0) comp. w/ rgb (1) comp. w/ yuv (x) y 3 luma green composite composite c 7 chroma blue red v ntsc/pal 1 11 composite composite green y ntsc/pal 2 15 composite red blue u hmp8170, hmp8171, hmp8172, hmp8173 14 composite + yuv output mode the hmp8172/hmp8173 also provide composite with component yuv output mode. when analog yuv video is selected, the hmp817x scales the filtered ycbcr data to match the levels required by its dacs. during the scaling, values less than 16 are clamped to 16. the scaling factors for cb and cr are the same, but the cbcr scaling factor is different from the y scaling factor. the encoder uses different sets of scale factors for ntsc and pal to accommodate their different black levels. the analog yuv outputs have a range of 0.3-1.0v with an optional blanking pedestal. composite sync information (0.0-0.3v) may be optionally added to the y output. vbi data is included on the y output. the hmp817x also generates composite video when in yuv output mode. all four outputs are time aligned. the output pin assignments are summarized in table 12. power down modes to reduce power dissipation, any of the four output dacs may be turned off. each dac has an independent enable bit. each output may be disabled in the host control register. when the power down mode is enabled, all of the dacs and internal voltage reference are powered down (forcing their outputs to zero) and the data pipeline registers are disabled. the host processor may still read from and write to the internal control registers. host interfaces reset the hmp817x resets to its default operating mode on power up, when the reset pin is asserted for at least four clk cycles, or when the software reset bit of the host control register is set. during the reset cycle, the encoder returns its internal registers to their reset state and deactivates the i 2 c interface. i 2 c interface the hmp817x provides a standard i 2 c interface and supports fast-mode (up to 400kbps) transfers. the device acts as a slave for receiving and transmitting data only. it will not respond to general calls or initiate a transfer. the encoders slave address is either 0100 000x b when the sa input pin is low or 0100 001x b when it is high. (the x bit in the address is the i 2 c read ?ag.) the i 2 c interface consists of the sda and scl pins. when the interface is not active, scl and sda must be pulled high using external 4-6k w pull-up resistors. the i 2 c clock and data timing is shown in figures 10 and 11. during i 2 c write cycles, the ?rst data byte after the slave address speci?es the sub address, and is written into the address register. only the seven lsbs of the subaddress are used; the msb is ignored. any remaining data bytes in the i 2 c write cycle are written to the control registers, beginning with the register speci?ed by the address register. the 7-bit address register is incremented after each data byte in the i 2 c write cycle. data written to reserved bits within registers or reserved registers is ignored. during i 2 c read cycles, data from the control register speci?ed by the address register is output. the address register is incremented after each data byte in the i 2 c read cycle. reserved bits within registers return a value of 0. reserved registers return a value of 00 h . the hmp817xs operating modes are determined by the contents of its internal registers which are accessed via the i 2 c interface. all internal registers may be written or read by the host processor at any time. however, some of the bits and words are read only or reserved and data written to these bits is ignored. table 13 lists the hmp817xs internal registers. their bit descriptions are listed in tables 14 through 45. table 13. control register names sub address (hex) control register reset condition 00 01 02 03 04 05 06 07 08-0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a-1f 20 21 22 23 24 25 26 27 28-2f 30-6a 6b-6f 70-7f product id output format input format video processing timing i/o 1 timing i/o 2 vbi data enable vbi data input reserved host control 1 host control 2 caption_21a caption_21b caption_284a caption_284b wss_20a wss_20b wss_283a wss_283b crc_20 crc_283 reserved start h_blank low start h_blank high end h_blank start v_blank low start v_blank high end v_blank field control 1 field control 2 reserved test and unused phase increment test and unused - 00 h 06 h 80 h 00 h 00 h 00 h 00 h - 1e h 00 h 80 h 80 h 80 h 80 h 00 h 00 h 00 h 00 h 3f h 3f h - 4a h 03 h 7a h 03 h 01 h 13 h 00 h 00 h - - - - hmp8170, hmp8171, hmp8172, hmp8173 15 figure 10. i 2 c serial timing flow figure 11. register write programming flow sda scl start condition s 1-7 address 8 r/w 9 ack 1-7 data 89 ack stop condition p a a s chip addr sub addr data data a ap s = start cycle p = stop cycle a = acknowledge from master from encoder 0x40 or data write data data data read register pointed to by subaddr register pointed to by subaddr na = no acknowledge 0x41 or p na a a chip addr s a sub addr a chip addr s 0x43 0x42 optional frame may be repeated n times optional frame may be repeated n times 0x40 or 0x42 table 14. product id register sub address = 00 h bit number function description reset state 7-0 product id this 8-bit register specifies the last two digits of the product number. it is a read-only register. data written to it is ignored. 70h 71h 72h 73h table 15. output format register sub address = 01 h bit number function description reset state 7-5 video timing standard 000 = (m) ntsc 001 = reserved 010 = (b, d, g, h, i) pal 011 = (m) pal 100 = (n) pal 101 = (nc) pal 110 = reserved 111 = reserved 000b 4-3 output format 00 = composite + y/c 01 = composite + yuv (hmp8172 and hmp8173 only) 10 = composite + rgb without sync on green (hmp8172 and hmp8173 only) 11 = composite + rgb with sync on green (hmp8172 and hmp8173 only) 00b 2-0 ntsc / pal setup select these bits specify the blanking pedestal during active video, from 0 ire (000) to 7.5 ire (111). typically, these bits should be a 111 during (m) ntsc and (m, n) pal operation. otherwise, they should be a 000. these bits do not affect the analog rgb or yuv outputs. 111b hmp8170, hmp8171, hmp8172, hmp8173 16 table 16. input format register sub address = 02 h bit number function description reset state 7-5 input format 000 = 16-bit 4:2:2 ycbcr 001 = 8-bit 4:2:2 ycbcr 010 = 8-bit bt.656 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved 000 b 4 - 0 reserved 00000 b table 17. video processing register sub address = 03 h bit number function description reset state 7 luminance processing 0 = none 1 = y lowpass filtering enabled 1 b 6 composite video limiting 0 = none 1 = lower limit of composite active video is about half the sync height 0 b 5 sch phase mode 0 = never reset sch phase 1 = reset sch phase every 4 (ntsc) or 8 (pal) fields 1 b 4 rgb / yuv setup select this bits specifies the blanking pedestal on the analog rgb and yuv outputs during active video. typically, this bit should be a 1 during (m) ntsc and (m, n) pal operation. otherwise, it should be a 0. this bit does not affect the analog composite or y/c outputs. 0 = 0 ire 1 = 7.5 ire 0 b 3 rgb output pins select this bit configures on what pins the analog rgb video is output. 0 = hmp8156 compatible 1 = scart compatible 0 b 2-0 reserved 000 b table 18. timing i/o register #1 sub address = 04 h bit number function description reset state 7 blank timing select this bit is ignored unless blank is configured to be an output. 0 = data for the first active pixel of the scan line must arrive the clk cycle after the encoder negates blank. 1 = data for the first active pixel of the scan line must arrive immediately after the encoder negates blank. 0 b 6 reserved 0 b 5 blank output control 0 = blank is an input 1 = blank is an output 0 b 4 blank polarity 0 = active low (low during blanking) 1 = active high (high during blanking) 0 b 3 hsync and vsync output control 0 = hsync and vsync are inputs 1 = hsync and vsync are outputs 0 b 2 hsync polarity 0 = active low (low during horizontal sync) 1 = active high (high during horizontal sync) 0 b 1 vsync polarity 0 = active low (low during vertical sync) 1 = active high (high during vertical sync) 0 b 0 field polarity 0 = active low (low during odd fields) 1 = active high (high during odd fields) 0 b hmp8170, hmp8171, hmp8172, hmp8173 17 table 19. timing i/o register #2 sub address = 05 h bit number function description reset state 7-6 reserved 00 b 5 clk polarity control 0 = inputs are sampled when clk is low (see table 2). 1 = inputs are sampled when clk is high. 0 b 4 clk output control 0 = clk is an input 1 = clk is an output 0 b 3 aspect ratio mode this bit must be set to 0 during bt.656 input mode. 0 = rectangular (bt.601) pixels 1 = square pixels 0 b 2 reserved 0 b 1-0 subcarrier phinc select selects the source of the color subcarrier nco phase increment value. 00 = internal (fixed) data. 01 = reserved 10 = bt.656 rtci ancillary data 11 = i 2 c interface phinc register 00 b table 20. auxiliary data enable register sub address = 06 h bit number function description reset state 7-6 closed captioning enable 00 = closed caption disabled 01 = closed caption enabled for odd fields: line 21 for ntsc, line 18 for (m) pal, or line 22 for (b, d, g, h, i, n, nc) pal 10 = closed caption enabled for even fields: line 284 for ntsc, line 281 for (m) pal, or line 335 for (b, d, g, h, i, n, nc) pal 11 = closed caption enabled for both odd and even fields 00 b 5-4 wss enable 00 = wss disabled 01 = wss enabled for odd fields: line 20 for ntsc; line 17 for (m) pal, or line 23 for (b, d, g, h, i, n, nc) pal 10 = wss enabled for even fields: line 283 for ntsc, line 280 for (m) pal, or line 336 for (b, d, g, h, i, n, nc) pal 11 = wss enabled for both odd and even fields 00 b 3 teletext enable 00 = teletext disabled 01 = system b teletext enabled 10 = system c teletext enabled 11 = reserved 00 b 1-0 reserved 00 b table 21. vbi data input register sub address = 07 h bit number function description reset state 7 closed caption line 21 bt.656 enable setting this bit enables bt.656 ancillary data to be written into the closed caption line 21 data registers. it is ignored unless in the bt.656 input mode. 0 = ignore bt.656 ancillary data 1 = use bt.656 ancillary data 0 b 6 closed caption line 284 bt.656 enable setting this bit enables bt.656 ancillary data to be written into the closed caption line 284 data registers. it is ignored unless in the bt.656 input mode. 0 = ignore bt.656 ancillary data 1 = use bt.656 ancillary data 0 b 5 wss line 20 bt.656 enable setting this bit enables bt.656 ancillary data to be written into the wss line 20 data registers. it is ignored unless in the bt.656 input mode. 0 = ignore bt.656 ancillary data 1 = use bt.656 ancillary data 0 b 4 wss line 283 bt.656 enable setting this bit enables bt.656 ancillary data to be written into the wss line 283 data registers. it is ignored unless in the bt.656 input mode. 0 = ignore bt.656 ancillary data 1 = use bt.656 ancillary data 0 b 3-0 reserved 0000 b hmp8170, hmp8171, hmp8172, hmp8173 18 table 22. host control register 1 sub address = 0e h bit number function description reset state 7-5 reserved 000 b 4 closed caption line 21 write status 0 = caption_21a and caption_21b data registers contain unused data 1 = data has been output, host processor may now write to the registers 1 b 3 closed caption line 284 write status 0 = caption_284a and caption_284b data registers contain unused data 1 = data has been output, host processor may now write to the registers 1 b 2 wss line 20 write status 0 = wss_20a, wss_20b, crc_20a, and crc_20b data registers contain unused data 1 = data has been output, host processor may now write to the registers 1 b 1 wss line 283 write status 0 = wss_283a and wss_283b data registers contain unused data 1 = data has been output, host processor may now write to the registers 1 b 0 reserved 0 b table 23. host control register 2 sub address = 0f h bit number function description reset state 7 software reset setting this bit to 1 initiates a software reset. it is automatically reset to a 0 after the reset sequence is complete. 0 b 6 general power down this bit powers down all dac outputs and most of the digital circuitry. 0 = normal operation 1 = power down mode 0 b 5 power down ntsc/pal 1 output dac this bit powers down only the ntsc/pal 1 dac output. 0 = normal operation 1 = power down mode 0 b 4 power down ntsc/pal 2 output dac this bit powers down only the ntsc/pal 2 dac output. 0 = normal operation 1 = power down mode 0 b 3 power down y output dac this bit powers down only the y dac output. 0 = normal operation 1 = power down mode 0 b 2 power down c output dac this bit powers down only the c dac output. 0 = normal operation 1 = power down mode 0 b 1-0 reserved 00 b table 24. closed caption_21a data register sub address = 10 h bit number function description reset state 7-0 line 21 caption lsb data this register is cascaded with the closed caption_21b data register and they are read out serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. bit d0 of the 21a data register is shifted out first. 80 h table 25. closed caption_21b data register sub address = 11 h bit number function description reset state 7-0 line 21 caption msb data this register is cascaded with the closed caption_21a data register and they are read out serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. bit d0 of the 21a data register is shifted out first. 80 h hmp8170, hmp8171, hmp8172, hmp8173 19 table 26. closed caption_284a data register sub address = 12 h bit number function description reset state 7-0 line 284 caption lsb data this register is cascaded with the closed caption_284b data register and they are read out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. bit d0 of the 284a data register is shifted out first. 80 h table 27. closed caption_284b data register sub address = 13 h bit number function description reset state 7-0 line 284 caption msb data this register is cascaded with the closed caption_284a data register and they are read out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. bit d0 of the 284a data register is shifted out first. 80 h table 28. wss_20a data register sub address = 14 h bit number function description reset state 7-0 line 20 wss lsb data this register is cascaded with the wss_20b data register and they are read out serially as 14 bits during line 17, 20, or 23 if wss is enabled. bit d0 of the wss_20a data register is shifted out first. 00 h table 29. wss_20b data register sub address = 15 h bit number function description reset state 7 - 6 reserved 00 b 5 - 0 line 20 wss msb data this register is cascaded with the wss_20a data register and they are read out serially as 14 bits during line 17, 20, or 23 if wss is enabled. bit d0 of the wss_20a data register is shifted out first. 000000 b table 30. wss_283a data register sub address = 16 h bit number function description reset state 7-0 line 283 wss lsb data this register is cascaded with the wss_283b data register and they are read out serially as 14 bits during line 280, 283, or 336 if wss is enabled. bit d0 of the wss_283a data register is shifted out first. 00 h table 31. wss_283b data register sub address = 17 h bit number function description reset state 7 - 6 reserved 00 b 5 - 0 line 283 wss msb data this register is cascaded with the wss_283a data register and they are read out serially as 14 bits during line 280, 283, or 336 if wss is enabled. bit d0 of the wss_283a data register is shifted out first. 000000 b table 32. crc_20 register sub address = 18 h bit number function description reset state 7-6 reserved 00 b 5-0 line 20 wss crc data this register is read out serially after the 14 bits of ntsc wss data, if wss is enabled. it is ignored during pal wss operation. bit d0 is shifted out first. 111111 b hmp8170, hmp8171, hmp8172, hmp8173 20 table 33. crc_283 register sub address = 19 h bit number function description reset state 7-6 reserved 00 b 5-0 line 283 wss crc data this register is read out serially after the 14 bits of ntsc wss data, if wss is enabled. it is ignored during pal wss operation. bit d0 is shifted out first. 111111 b table 34. start h_blank low register sub address = 20 h bit number function description reset state 7-0 lsb assert blank output signal (horizontal) this 8-bit register is cascaded with start h_blank high register to form a 10-bit start_horizontal_blank register. it specifies the horizontal count (in 1x clock cycles) at which to start ignoring pixel data each scan line. the leading edge of hsync is count 020 h . this register is ignored unless blank is configured as an output. 4a h table 35. start h_blank high register sub address = 21 h bit number function description reset state 7-2 reserved 000000 b 1-0 msb assert blank output signal (horizontal) this 2-bit register is cascaded with start h_blank low register to form a 10-bit start_horizontal_blank register. it specifies the horizontal count (in 1x clock cycles) at which to start ignoring pixel data each scan line. the leading edge of hsync is count 020 h . this register is ignored unless blank is configured as an output. 11 b table 36. end h_blank register sub address = 22 h bit number function description reset state 7-0 negate blank output signal (horizontal) this 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting pixel data each scan line. the leading edge of hsync is count 000 h . this register is ignored unless blank is configured as an output. 7a h table 37. start v_blank low register sub address = 23 h bit number function description reset state 7-0 lsb assert blank output signal (vertical) this 8-bit register is cascaded with start v_blank high register to form a 9-bit start_vertical_blank register. during normal operation, it specifies the line number (n) to start ignoring pixel input data (and what line number to start blanking the output video) each odd field; for even fields, it occurs on line (n + 262) or (n + 313). the leading edge of vsync at the start of an odd field is count 000 h (note that this does not follow standard ntsc or pal line numbering). this register is ignored unless blank is configured as an output. 03 h hmp8170, hmp8171, hmp8172, hmp8173 21 table 38. start v_blank high register sub address = 24 h bit number function description reset state 7-1 reserved 0000000 b 0 msb assert blank output signal (vertical) this 1-bit register is cascaded with start v_blank low register to form a 9-bit start_vertical_blank register. this register is ignored unless blank is configured as an output. 1 b table 39. end v_blank register sub address = 25 h bit number function description reset state 7-0 negate blank output signal (vertical) during normal operation, this 8-bit register specifies the line number (n) to start inputting pixel input data (and what line number to start generating active output video) each odd field; for even fields, it occurs on line (n + 262) or (n + 313). the leading edge of vsync at the start of an odd field is count 000 h (note that this does not follow standard ntsc or pal line numbering). this register is ignored unless blank is configured as an output. 13 h table 40. field control register 1 sub address = 26 h bit number function description reset state 7-0 field detect window size low this 8-bit register is cascaded with field detect window size high to form a 9-bit field detect window size value. the value specifies the number of 1x clock cycles in the detection window before and after the selected edge of vsync. it may range from 0 to 511. if the leading edge of hsync occurs within the window, it is the start of an odd or even field, as specified by the field detect select bit. this register is ignored unless hsync and vsync are configured as inputs. 80 h table 41. field control register 2 sub address = 27 h bit number function description reset state 7-4 half line count reset value these bits specify the value to load to the vertical half line counter when the selected edge of vsync. the value is ignored when hsync and vsync are configured as outputs. 00000 b 2 vsync edge select this bit specifies whether the encoder uses the leading or trailing edge of vsync to determine the field and to reset the half line counter. it is ignored unless hsync and vsync are configured as inputs. 0 = leading edge 1 = trailing edge 0 b 1 field detect select this bit specifies whether an odd or even field is starting when the leading edge of hsync occurs within the field detect window. it is ignored unless hsync and vsync are configured as inputs. 0 = odd field 1 = even field 0 b 0 field detect window size high this bit is cascaded with field detect window size low to form a 9-bit field detect window size value. this bit is ignored unless hsync and vsync are configured as inputs. 0 b hmp8170, hmp8171, hmp8172, hmp8173 22 table 42. phase increment register 0 sub address = 6b h bit number function description reset state 7-0 phinc 0 (lsb) the 8-bit registers phinc 0C3 are cascaded together to form a 32-bit phinc value. the phinc value is the phase increment value of the color subcarrier generation nco. when the bt.656 ancillary data is selected as the phinc source, the phinc registers may be read to determine the last phinc value loaded via the selected interface. 00 h table 43. phase increment register 1 sub address = 6c h bit number function description reset state 7-0 phinc 1 the 8-bit registers phinc 0C3 are cascaded together to form a 32-bit phinc value. the phinc value is the phase increment value of the color subcarrier generation nco. when the bt.656 ancillary data is selected as the phinc source, the phinc registers may be read to determine the last phinc value loaded via the selected interface. 00 h table 44. phase increment register 2 sub address = 6d h bit number function description reset state 7-0 phinc 2 the 8-bit registers phinc 0C3 are cascaded together to form a 32-bit phinc value. the phinc value is the phase increment value of the color subcarrier generation nco. when the bt.656 ancillary data is selected as the phinc source, the phinc registers may be read to determine the last phinc value loaded via the selected interface. 00 h table 45. phase increment register 1 sub address = 6e h bit number function description reset state 7-0 phinc 3 (msb) the 8-bit registers phinc 0C3 are cascaded together to form a 32-bit phinc value. the phinc value is the phase increment value of the color subcarrier generation nco. when the bt.656 ancillary data is selected as the phinc source, the phinc registers may be read to determine the last phinc value loaded via the selected interface. 00 h hmp8170, hmp8171, hmp8172, hmp8173 23 pinout hmp817x (pqfp) top view 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 comp 1 comp 2 fs_adjust vref gnd gnd p0 vaa gnd p1 p2 p3 p4 p5 p6 p7 vaa vaa y c gnd vaa gnd ntsc/pal1 gnd gnd ntsc/pal2 gnd vaa gnd gnd vaa scl sda sa resv nc nc vaa reset gnd nc nc nc nc nc nc gnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p8 p9 p10 p11 p12 p13 gnd clk2 vaa clk p14 p15 vsync hsync field blank pin descriptions pin name pin number input/ output description p0-p15 58, 55-43, 38, 37 i pixel input pins. see table 1. any pixel inputs not used should be connected to gnd. nc 32-27, 23, 22 i no connect pins. these pins are not used. they may be left floating or may be connected to gnd. resv 21 i this pin is reserved and should be connected to gnd. field 34 o field output. the field output indicates that the encoder is outputting the odd or even video field. the polarity of field is programmable. hsync 35 i/o horizontal sync input/output. as an input, this pin must be asserted during the horizontal sync intervals. if it occurs early, the line time will be shortened. if it occurs late, the line time will be lengthened by holding the outputs at the front porch level. as an output, it is asserted during the horizontal sync intervals. the polarity of hsync is programmable. if not driven, the circuit for this pin should include a 4-12k w pull up resistor connected to vaa. vsync 36 i/o vertical sync input/output. as an input, this pin must be asserted during the vertical sync intervals. if it occurs early, the field time will be shortened. if it occurs late, the field time will be lengthened by holding the outputs at the blanking level. as an output, it is asserted during the vertical sync intervals. the polarity of vsync is programmable. if not driven, the circuit for this pin should include a 4-12k w pull up resistor connected to vaa. blank 33 i/o composite blanking input/output. as an input, this pin must be asserted during the horizontal and vertical blanking intervals. as an output, it is asserted during the horizontal and vertical blanking intervals. the polarity of blank is programmable. if not driven, the circuit for this pin should include a 4-12k w pull up resistor connected to vaa. hmp8170, hmp8171, hmp8172, hmp8173 24 clk 39 i/o 1x pixel clock input/output. as an input, this clock must be free-running and synchronous to the clock signal on the clk2 pin. as an output, this pin may drive a maximum of one ls ttl load. clk is generated by dividing clk2 by two or four, depending on the mode. if not driven, the circuit for this pin should include a 4-12k w pull up resistor connected to vaa. clk2 41 i 2x pixel clock input. this clock must be a continuous, free-running clock. scl 18 i i 2 c interface clock input. the circuit for this pin should include a 4-6k w pull-up resistor connected to vaa. sa 19 i i 2 c interface address select input. sda 20 i/o i 2 c interface data input/output. the circuit for this pin should include a 4-6k w pull-up resistor connected to vaa. reset 25 i reset control input. a logical zero for a minimum of four clk cycles resets the device. reset must be a logical one for normal operation. y 3 o luminance analog current output. this output contains luminance video, sync, blanking, and information. in analog yuv or rgb output mode, an alternate signal is generated (see table 12). it is capable of driving a 37.5 w load. if not used, it should be connected to gnd. c 7 o chrominance analog current output. this output contains chrominance video, and blanking information. in analog yuv or rgb output mode, an alternate signal is generated (see table 12). it is capable of driving a 37.5 w load. if not used, it should be connected to gnd. ntsc/pal 1 11 o composite video analog current output. this output contains composite video, sync, blanking, and information. in analog yuv or rgb output mode, an alternate signal is generated (see table 12). it is capable of driving a 37.5 w load. if not used, it should be connected to gnd. ntsc/pal 2 15 o composite video analog current output. this output contains composite video, sync, blanking, and information. in analog yuv or rgb output mode, an alternate signal is generated (see table 12). it is capable of driving a 37.5 w load. if not used, it should be connected to gnd. vref 61 i/o voltage reference. an optional external 1.235v reference may be used to drive this pin. if left floating, the internal voltage reference is used. fs_adjust 62 full scale adjust control. a resistor (rset) connected between this pin and gnd sets the full-scale output current of each of the dacs. comp 1 64 compensation pin. a 0.1 m f ceramic chip capacitor should be connected between this pin and vaa, as close to the device as possible. comp 2 63 compensation pin. a 0.1 m f ceramic chip capacitor should be connected between this pin and vaa as close to the device as possible. vaa +5v power. a 0.1 m f ceramic capacitor, in parallel with a 0.01 m f chip capacitor, should be used between each group of vaa pins and gnd. these should be as close to the device as possible. gnd ground pin descriptions (continued) pin name pin number input/ output description hmp8170, hmp8171, hmp8172, hmp8173 25 absolute maximum ratings thermal information supply voltage (v aa to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0v all signal pins . . . . . . . . . . . . . . . . . . . . . (gnd C 0.5v) to (v aa + 0.5v) esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 4) q ja o c/w pqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c vapor phase soldering, 1 minute . . . . . . . . . . . . . . . . . . . . . .220 o c (pqfp - lead tips only) caution: stresses above those listed in the absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and opera tion of the device at these or any other conditions above those indicated in the operation section of this speci?cation is not implied. note: 4. q ja is measured with the component mounted on an evaluation printed circuit board in free air. dissipation rating assumes that the device is mounted with all its leads soldered to the pcb. electrical speci?cations v aa = +5v 5%, rset = 133 w , vref unconnected, t a = 25 o c, unless otherwise specified parameter test condition min typ max units dc parameters, digital inputs except clk2, sda, scl input logic low voltage, v il - - 0.8 v input logic high voltage, v ih 2.0 - - v input logic low current, i il v in = 0.0v - - -10 m a input logic high current, i ih v in = v aa --10 m a input capacitance, c in -8-pf dc parameters, clk2 input input logic low voltage, v il - - 0.3 x v aa v input logic high voltage, v ih 0.7 x v aa --v input logic low current, i il v in = 0.0v - - -10 m a input logic high current, i ih v in = v aa --10 m a input capacitance, c in -8-pf dc parameters, sda and scl inputs input logic low voltage, v il - - 0.3 x v aa v input logic high voltage, v ih 0.7 x v aa --v input current, i i v in = 0.0v C v aa -- 10 m a input capacitance, c in -8-pf dc parameters, digital outputs, except sda output logic low voltage, v ol i ol = 2ma - - 0.4 v output logic high voltage, v oh i oh = -2ma 2.4 - - v output capacitance, c out -8-pf dc parameters, sda output output logic low voltage, v ol i ol = 3ma - - 0.4 v output capacitance, c out -8-pf dc parameters, analog outputs dac resolution - 10 - bits integral nonlinearity, inl - 0.5 2 lsb differential nonlinearity, dnl - 0.5 1 lsb output current - - 34.8 ma output impedance i out = 0ma - 2m - w i out = 34ma - 300k - w output capacitance i out = 0ma, clk = 13.5mhz - 15 - pf output compliance range 0 - 1.4 v hmp8170, hmp8171, hmp8172, hmp8173 26 video level error (note 5) internal voltage reference vref unconnected, rset = 133 w -- 10 % external voltage reference vref = 1.230v (figure 27), rset = 140 w -- 10 % dac to dac matching --5% vref output voltage pin not connected, using internal reference 1.13 1.19 1.32 v vref output current -50 - 50 m a vref input voltage pin connected to external reference shown in figure 27. 1.11 1.23 1.36 v vref input current -500 - 500 m a ac parameters, analog outputs differential gain error using analog output filter shown in figure 28a. - 1 - % differential phase error - 1 - degree snr (weighted) -70-db hue accuracy - 2 - degree color saturation accuracy -2-% luminance nonlinearity -1-% residual subcarrier - -60 - db sch phase sch phase reset enabled - 1.5 - degree analog output skew, t ask --3ns analog output delay, t ad - - 12 ns dac-dac crosstalk - -60 - db glitch energy using analog output filter shown in figure 28a. includes clock and data feedthrough - 35 - pv-s ac parameters, digital inputs and outputs except scl and sda setup time, t s note 6. 8 - - ns hold time, t h 0- -ns clk2 to output delay, t d 3 - 15 ns clk2 frequency - - 30.0 mhz clk2 high time, clk2 h 13.6 - 20.3 ns clk2 low time, clk2 l 13.6 - 20.3 ns reset* pulse width low, t res 4 - - clk cycles ac parameters, scl and sda (i 2 c interface) all ac parameters meet the fast-mode i 2 c bus interface specification. power supply characteristics dac psrr at dc note 7 - 64 - db power supply range, v aa 4.75 5.0 5.25 v normal supply current, i aa - - 260 ma power-down supply current, i aa note 8 - - 750 m a power dissipation - 1100 1300 mw notes: 5. output level is dependent on the voltage on vref, the value of rset, and the load. 6. test performed with c l = 40pf, i o = 2ma, v ih = 3.0v, v il = 0.0v. input reference level is 2.0v for all inputs. 7. the supply voltage rejection is the relative variation of the full-scale output driving a 37.5 w load for a 5% supply variation: psrr = 20 x log ( d v aa / d v out ). 8. if using an external voltage reference, it is not powered down. the internal voltage reference is powered down. electrical speci?cations v aa = +5v 5%, rset = 133 w , vref unconnected, t a = 25 o c, unless otherwise specified (continued) parameter test condition min typ max units hmp8170, hmp8171, hmp8172, hmp8173 27 typical performance curves figure 12. noise spectrum (ntsc) figure 13. ntsc color bar vector scope plot figure 14. ntsc fcc color bar 1.0 2.0 3.0 4.0 5.0 (mhz) average 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 field = 1 line = 47 amplitude (0db = 714mv p-p ) bandwidth 10khz to full wfm ---> pedestal noise level = -79.9db rms apl = 44.3% system line l 47 f1 angle (deg) 0.0 gain x1.000 0.000db 525 line ntsc burst from source setup 7.5% hmp8170, hmp8171, hmp8172, hmp8173 28 figure 15. luminance non linearity (ntsc) figure 16. line frequency (ntsc) figure 17. h sync jitter in a frame (ntsc) figure 18. sch phase measurement figure 19. noise spectrum (pal) figure 20. pal color bar vector scape plot typical performance curves (continued) 97.9 99.1 99.1 99.8 100.0 105.0 104.5 104.0 103.5 103.0 102.5 102.0 101.5 101.0 100.5 100.0 99.5 99.0 98.5 98.0 97.5 97.0 96.5 96.0 95.5 95.0 1st 2nd 3rd 4th 5th average field = 1 line = 47 luminance non linearity (%) wfm ---> 5 step peak-to-peak = 2.1 0.00 (%) -0.4 -0.2 0.0 0.2 0.4 line frequency 15.734 (khz) field frequency 59.94 (hz) line frequency error average off (%) line jitter (line 20 to 250) 2ns p-p 525 line ntsc mean sch 0.8 degrees average average apl = 40.0% system line l 72 angle (deg) 0.0 gain x1.000 0.000db 625 line pal burst from source display +v and -v hmp8170, hmp8171, hmp8172, hmp8173 29 figure 21. colorbar (pal) figure 22. luminance non linearity (pal) figure 23. line frequency (pal) typical performance curves (continued) line = 72 wfm ---> color bar 97.9 99.1 99.1 99.8 100.0 105.0 104.5 104.0 103.5 103.0 102.5 102.0 101.5 101.0 100.5 100.0 99.5 99.0 98.5 98.0 97.5 97.0 96.5 96.0 95.5 95.0 1st 2nd 3rd 4th 5th average line = 72 luminance non linearity (%) wfm ---> 5 step peak-to-peak = 1.4 0.00 (%) -0.4 -0.2 0.0 0.2 0.4 line frequency 15.625 (khz) field frequency 50.00 (hz) line frequency error average off (%) hmp8170, hmp8171, hmp8172, hmp8173 30 application information pcb considerations a pcb board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. the pcb layout should implement the lowest possible noise on the power and ground planes by providing excellent decoupling. pcb trace lengths between groups of v aa and gnd pins should be as short as possible. component placement the optimum layout places the hmp817x at the edge of the pcb and as close as possible to the video output connector. external components should be positioned as close as possible to the appropriate pin, ideally such that traces can be connected point to point. chip capacitors are recommended where possible, with radial lead ceramic capacitors the second-best choice. traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize crosstalk. if this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the analog signals. the analog output traces should also not cross over or under the v cc power plane to maximize high- frequency power supply rejection. power and ground planes a common ground plane for all devices, including the hmp817x, is recommended. however, placing the encoder on an electrically connected gnd peninsula reduces noise levels. all gnd pins on the hmp817x must be connected to the ground plane. typical power and ground planes are shown in figure 26. the small connection between the ground areas should be made wide enough so that most of the encoders digital inputs can be routed over or under it. it is especially important that the clk and clk2 signals cross through the connection. the hmp817x should have its own power plane that is isolated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. all v aa pins of the hmp817x must be connected to this isolated power plane. the hmp817x power plane should be connected to the boards normal v cc power plane at a single point though a low-resistance ferrite bead, such as a ferroxcube 5659065-3b, fair-rite 2743001111, or tdk bf45-4001. the ferrite bead provides resistance to switching currents, improving the performance of hmp817x. a single, large capacitor should also be used between the hmp817x power plane and the ground plane to control low-frequency power supply ripple. figure 24. h sync jitter in a frame (pal) figure 25. sch phase measurement typical performance curves (continued) hmp8170, hmp8171, hmp8172, hmp8173 31 for proper operation, power supply decoupling is required. it should be done using a 0.1 m f ceramic capacitor in parallel with a 0.01 m f chip capacitor for each group of v aa pins to ground. these capacitors should be located as close to the v aa and gnd pins as possible, using short, wide traces. if a separate linear regulator is used to provide power to the hmp817x power plane, the power-up sequence should be designed to ensure latchup will not occur. a separate linear regulator is recommended if the power supply noise on the vaa pins exceeds 200mv. about 10% of the noise (that is less than 1mhz) on the vaa pins will couple onto the analog outputs. external reference voltage if an external reference voltage is used, its circuitry should receive power from the same plane as the hmp817x. the external vref must also be stable and well decoupled from the power plane. an example vref circuit using a band gap reference diode is shown in figure 27. figure 26a. v cc and v aa planes figure 26b. common ground plane figure 26. example power and ground planes lp vcc vaa ferrite bead bulk area capacitor 8154/8156a pcb analog filters conn. lp vcc vaa ferrite bead bulk area capacitor 817x pcb analog filters conn. lp gnd 8154/8156a pcb analog filters conn. lp gnd 817x pcb analog filters conn. hmp8170, hmp8171, hmp8172, hmp8173 32 analog output filters the various video standards specify the frequency response of the video signal. the hmp817x uses 2x oversampling dacs to simplify the reconstruction ?lter required. example post ?lters are shown in figure 28. the analog output ?lters should be as close as possible to the hmp817x. evaluation kits the hmp817xeval1 is a small (index card size) printed circuit board containing the encoder, voltage references and bypassing, analog output ?lters, and input/output connectors. the board allows the encoders operation and performance to be observed and measured. the hmp817xeval1 board has a 50 pin, two row receptacle which allows connection into an existing system. the connector provides access to all of the encoders digital inputs and outputs. the hmp8156eval2 is the intersil designed mother board for the hmp817xeval1. the mother board is a standard size pc add in card with an isa bus interface and application software. the hmp8156eval2 kit is a complete system which allows demonstrating all of both encoders operating modes. it has analog video inputs for composite, s-video, and component rgb signals. the analog signals are converted/decoded to the digital domain and input to the encoder. the board also provides a 3 megabyte video ram for image capture and display and a bt.656 connector and interface. for simpler operation, the hmp817xeval1 may also be driven by external power supplies, a bt.656 signal generator, and a pc parallel port. the evaluation kit includes application software to program the part using its i 2 c bus connected to the printer port. the board includes the standard 25 pin bt.656 connector and interface. figure 27. external reference voltage circuit 0.01 m f + 4.7 m f vaa 1.235v icl8069 6.8k figure 28a. high quality filter figure 28b. low cost filter figure 28. example post-filter circuits rl 75 1.0 m h 82pf 2.2 m h 330pf 1.0 m h 39pf 330pf 75 rl 75 2.7 m h 560pf 560pf 75 hmp8170, hmp8171, hmp8172, hmp8173 33 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hmp8170, hmp8171, hmp8172, hmp8173 metric plastic quad flatpack packages (mqfp/pqfp) d d1 e e1 -a- pin 1 a2 a1 a 5 o -16 o 5 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.10 0.004 -c- -d- -h- q64.14x14 (jedec mo-108bd-2 issue a) 64 lead metric plastic quad flatpack package sym- bol inches millimeters notes min max min max a - 0.130 - 3.30 - a1 0.004 0.010 0.10 0.25 - a2 0.100 0.120 2.55 3.05 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.667 0.687 16.95 17.45 3 d1 0.547 0.555 13.90 14.10 4, 5 e 0.667 0.687 16.95 17.45 3 e1 0.547 0.555 13.90 14.10 4, 5 l 0.026 0.037 0.65 0.95 - n64 647 e 0.032 bsc 0.80 bsc - rev. 0 1/94 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and tolerances per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. n is the number of terminal positions. -c- -h- |
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